1. Field of the Invention
The present invention relates, generally, to the processing of interrupts by a host, and in particular embodiments, to an interrupt notification block that is writeable by a host interface port and readable by the host to reduce the overhead that is involved when the host processes interrupts or has to read information across the host bus.
2. Description of Related Art
A generalized representation of an exemplary conventional computing system is illustrated in FIG. 1. A computer or server identified generally herein as a host 100 is connected to a host bus 102 (e.g. a PCI-X bus). The host 100 typically includes one or more host processors 114, cache 116, and main memory 132. Also attached to the host bus 102 is at least one port (e.g. a host bus adapter (HBA), an I/O controller, or the like), which is configured by its firmware as an interface to the host 100 and referred to generally herein as a host interface port 104. The host 100 and the host interface ports 104 may all reside within the same chassis. The host 100 and the host interface port 104 must frequently communicate over the host bus 102. For example, the host 100 may ask for service from the host interface port 104 via a command, or configure itself to receive asynchronous information, and be notified when the asynchronous information is available or when the commands have been completed. To facilitate these communications, the host 100 includes a command ring 108 and a response ring 110 in main memory 132, which may comprise a circular queue or other data structure that performs a similar function. In general, rings are used to pass information across the host bus 102 from the host 100 to the host interface port 104, or vice versa.
The command ring 108 stores command representations such as command I/O control blocks (IOCBS) 148 that are to be presented to the host interface port 104. A command IOCB 148 contains all of the information needed by the host interface port 104 to carry out a command. When the host 100 writes a command IOCB 148 into the command ring 108, it also increments a put pointer 144 to indicate that a new command IOCB 148 has been placed into the command ring 108. When the host interface port 104 reads a command IOCB 148 from the command ring 108, it increments a get pointer 146 to indicate that a command IOCB 148 has been read from the command ring 108. In general (excluding for the moment the fact that the command ring 108 is a circular ring that wraps around), if the put pointer 144 is equal to the get pointer 146, the command ring 108 is empty. If the put pointer 144 is ahead of the get pointer 146, there are commands 148 in the command ring 108 to be read by the host interface port 104. If the put pointer 144 is one less than the get pointer 146, the command ring 108 is full.
The response ring 110 stores response indicators such as response IOCBs 156 of asynchronous events written by the host interface port 104, including notifications of command completions and of unexpected events. Response IOCBs 156 contain all of the information needed by the host 100 to recognize the completed commands or to handle the unexpected events. For example, one such response IOCB 156 may require that the host 100 initiate a new command. When the host interface port 104 writes a response IOCB 156 into the response ring 110, it also increments a put pointer 150 to indicate that a new response IOCB 156 has been placed into the response ring 110. When the host 100 reads a response IOCB 156 from the response ring 110, it increments a get pointer 152 to indicate that a response IOCB 156 has been read from the response ring 110.
The host 100 also includes a collection of pointers such as a port pointer array 106 in main memory 132. The port pointer array 106 contains a list of pointers that can be updated by the host interface port 104. These pointers are entry indexes into the command ring 108, response ring 110, and other rings in the host 100. For example, the port pointer array 106 contains the get pointer 146 for the command ring 108 and the put pointer 150 for the response ring 110. When updated, these pointers indicate to the host 100 that a command IOCB 148 has been read from the command ring 108 by the host interface port 104, or that a response IOCB 156 has been written into the response ring 110 by the host interface port 104.
The host interface port 104 includes a host bus configuration area 126. The host bus configuration area 126 contains information that allows the host 100 to identify the type of host interface port 104 and what its characteristics are, and to assign base addresses to the host interface port 104 so that programs can talk to the host interface port 104.
The host interface port 104 also includes a collection of pointers such as a host pointer array 128. The host pointer array 128 contains a list of pointers that can be updated by the host 100. These pointers are entry indexes into the command ring 108, response ring 110, and other rings in the host 100. For example, the host pointer array 128 contains the put pointer 144 for the command ring 108 and the get pointer 152 for the response ring 110. When updated, these pointers indicate to the host interface port 104 that a command IOCB 148 has been written into the command ring 108 by the host 100, or that a response IOCB 156 has been read from the response ring 110 by the host 100. Note that it is relatively inexpensive, from a computational efficiency and overhead standpoint, for the host 100 to initiate writes over the host bus 102, because once the host 100 puts the data onto the host bus 102 (a “posted write”), no acknowledgement is sent, so the host 100 can proceed with the execution of further instructions without waiting for the write operation to complete.
The host interface port 104 also includes structures such as interface registers 118, which include a host attention register 120, a host control register 122, a host status register 124, and a mailbox register 154. The host control register 122 is configurable by the host 100 and contains interrupt enables that identify those attention conditions for which the host 100 would like to receive an interrupt. The host attention register 120 is a concise bitmap of attention conditions of interest to the host 100. For example, these attention conditions may indicate that there has been an update to the response ring put pointer 150 (which indicates that new responses are available), a link attention condition has occurred, a mailbox operation has completed, or an error condition has occurred.
When the host interface port 104 has completed the processing of a command from the host 100, the host interface port 104 first examines the get pointer 152 for the response ring 110 stored in the host pointer array 128 and compares it to the known put pointer 150 for the response ring 110 in order to determine if there is space available in the response ring 110 to write a response entry 156. If there is space available, the host interface port 104 becomes master of the host bus 102 and performs a direct memory access (DMA) operation to write a response IOCB 156 into the response ring 110, and performs another DMA operation to update the put pointer 150 in the port pointer array 106, indicating that there is a new response IOCB 156 to be processed in the response ring 110. The host interface port 104 then writes the appropriate attention conditions into the host attention register 120, and triggers the generation of an interrupt, if interrupts have been enabled by the host 100 in the host control register 122.
When an interrupt is received by the host 100 from the host interface port 104, the host 100 must execute an interrupt handler and a handler for the particular host interface port that initiated the interrupt. The host 100 then initiates a read of the host attention register 120 in the host interface port 104 to determine how to proceed with the interrupt. It is expensive, from a computational efficiency standpoint, for the host 100 to go out over the host bus 102 and read the host attention register 120 in the host interface port 104, because the host 100 must wait for the operation currently being executed in the host 100 to complete (which may take a long time), other host programs currently being executed must be placed on hold, information from the programs currently being executed must be saved off, the interrupting host interface port must be identified, registers for processing the interrupt must be set up, and the host attention register 120 must be read across the host bus 102 and any other intervening buses to determine the condition being reported so that the host 100 can respond accordingly. While the host attention register 120 is being read, no other processing is occurring in the host 100. In addition, the host 100 may have to arbitrate with other requesters. In multi-processor systems, a processor may also have to acquire a “lock” which enables that processor to handle the interrupt.
As described above, the contents of the host attention register 120 indicate to the host 100 what has been changed (e.g. a new response has been written into the response ring 110), and once notified, the host computer can process the change (e.g. read the response and react accordingly). Once the host 100 has called the appropriate routine to process the interrupt, it can write to the host interface port 104 and clear down those attention conditions in the host attention register 120 that the host 100 is currently handling.
One known method of reducing the number of interrupts that the host 100 must process is called interrupt coalescing. Interrupt coalescing is a request by the host 100 that it not be sent interrupts if it has already performed some processing of responses. If interrupt coalescing is enabled, when the host interface port 104 performs DMA operations to write a response IOCB 156 into the response ring 110 and update the put pointer 150 in the port pointer array 106, it does not automatically write the appropriate attention conditions into the host attention register 120. To do so would automatically trigger the generation of an interrupt, if interrupts are enabled in the host control register 122. Instead, the host 100 is given an opportunity to read the pointers in the port pointer array 106 and read and process the next response IOCB 156 in the response ring 110 when it has an opportunity to do so. After a predetermined amount of time has passed or a predetermined number of response IOCBs 156 have been written into the response ring 110 by the host interface port 104, the host interface port 104 reads the host pointer array 128, and if the pointers in the host pointer array 128 indicate that the host 100 is reading response IOCBs 156 from the response ring 110 and making progress in responding to the attention conditions that would ordinarily give rise to an interrupt, then the host interface port 104 may defer writing attention conditions to the host attention register 120 and initiating an interrupt. If, on the other hand, the predetermined amount of time has passed or the predetermined number of response IOCBs 156 have been written by the host interface port 104 into the response ring 110, but no progress by the host 100 is indicated by the host pointer array 128, the host 100 needs to be awakened. The host interface port 104 writes the appropriate attention condition information into the host attention register 120 and an interrupt is generated. When the host 100 receives the interrupt, it must incur the expense of reading the host attention register 120 of the host interface port 104 that sent the interrupt.
Despite the improvements in overhead that are possible with interrupt coalescing, there is still a need to further reduce the overhead that is involved when the host processes interrupts or has to read information across the host bus.